Three-Phase Trinary Asymmetric Multilevel Inverter With Single DC Source and Open-Loop Control

被引:11
|
作者
Vasu, Rajesh [1 ]
Chattopadhyay, Sumit Kumar [2 ]
Chakraborty, Chandan [1 ]
机构
[1] Indian Inst Technol Kharagpur, Dept Elect Engn, Kharagpur 721302, India
[2] Indian Inst Technol Delhi, Ctr Energy Studies, New Delhi 110016, India
关键词
Capacitors; Topology; Multilevel inverters; Bridge circuits; Voltage control; Redundancy; Modulation; Capacitor-balancing; trinary asymmetric multilevel inverter; space-vector; TOPOLOGY; PWM;
D O I
10.1109/OJIA.2021.3105605
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A three-phase trinary-asymmetric cascaded H-bridge multilevel inverter topology with single dc source per phase is presented in this paper. Only one of the H-bridges (called Main bridge) is fed from a dc source and all others (called auxiliary bridges) derive their dc links from floating capacitors. Existing literature mostly depend on closed loop control schemes to stabilize the dc link voltage. This paper proposes a new open loop control strategy for balancing of voltage across floating capacitors naturally. The dc bus voltages of auxiliary bridges are converged to maintain a trinary asymmetric ratio with the main-bridge by selecting the right set of space-vectors. Modulation of the inverter is carried out by exploring the space-vector redundancies that will help in achieving natural balancing of capacitor voltages. Selection of number of bridges to be cascaded, depends on criteria such as the allowable time of convergence, number of switching devices, acceptable power quality indices etc. Considering such constraints, a system with three cascaded cells per phase is found to exhibit satisfactory performances. Hence in this paper, simulation results obtained in MATLAB/Simulink based model corresponding to such a system are presented. Experimental results observed on a laboratory prototype matched well with the simulation.
引用
收藏
页码:259 / 277
页数:19
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