Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA

被引：18

作者：

Hu, Bo ^{[1
]}

Tian, Jingxiang ^{[1
]}

Shihab, Mustafa ^{[1
]}

Reddy, Gaurav Rajavendra ^{[1
]}

Swartz, William ^{[1
]}

Makris, Yiorgos ^{[1
]}

Schaefer, Benjamin Carrion ^{[1
]}

Sechen, Carl ^{[1
]}

机构：

[1] Univ Texas Dallas, Dept Elect Comp Engn, Richardson, TX 75080 USA

来源：

GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI | 2019年

关键词：

hardware security; obfuscation; high level synthesis; embedded FPGA;

D O I：

10.1145/3299874.3317992

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The protection of Intellectual Property (IP) has emerged as one of the most serious areas of concern in the semiconductor industry. To address this issue, we present a method and architecture to map selective portions of a design, given as a behavioral description for High-Level Synthesis (HLS) to a high-security embedded Field-Programmable Gate Array (eFPGA). In this manner, only the end-user has access to the full functionality of the chip. Using six benchmark circuits, we show that our approach is effective. In all cases, the Time-To-Break (TTB) is so long (at least 8 million hours) that for all practical purposes the designs are secure, while incurring area overheads of around 5%. Further, latencies were only slightly increased, while the computation times are under one minute.

引用

页码：171 / 176

页数：6