A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier

被引：4
|
作者：
Radjen, Dejan [1 ]
Anderson, Martin [2 ]
Sundstrom, Lars [2 ]
Andreani, Pietro [1 ]
机构：
[1] Lund Univ, S-22100 Lund, Sweden
[2] Ericsson AB, S-22183 Lund, Sweden
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2014年 / 80卷 / 03期
关键词：
Delta-Sigma; Single-operational-amplifier; Low-power; Continuous time; RC loop filter; COMPENSATION; SNDR;
D O I：
10.1007/s10470-014-0335-8
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We present a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) employing a 2nd-order loop filter with a single operational amplifier. This choice strongly reduces the power consumption, since operational amplifiers are the most power hungry blocks in the DSM. The DSM has been implemented in a 65 nm CMOS process, where it occupies an area of . It achieves an SNDR of 64 dB over a 500 kHz signal bandwidth with an oversampling ratio of 16. The power consumption is from a 800 mV power supply. The DSM figure-of-merit is 59 fJ/conversion. The CT DSM is well suited for the receiver of an ultra-low-power radio.
引用
收藏
页码：387 / 397
页数：11
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