High-performance damascene-gate thin film transistors

We report a novel TFT structure where the gate metal is embedded into a SiNx passivation layer. This allows the subsequent gate dielectric layer to be much thinner than in conventional bottom-gate structures. thereby reducing the threshold voltage and the sub-threshold slope. TFTs employing these damascene-gate structures were fabricated with SiNx gate dielectrics as thin as 50 nm, Such devices exhibit threshold voltages of 0.9 V, sub-threshold slopes of 0.1 V/dec, I-ON/I-OFF current ratios of 10(6) and linear region field-effect mobilities of 0.6 cm(2)/V s.