A 5-GHz Adjustable Loop Bandwidth Frequency Synthesizer With an On-Chip Loop Filter Array

被引：10
|
作者：
Kuo, Yue-Fang [1 ]
Yang, Ming-Hsien [1 ]
Chiang, Yi-Chien [1 ]
机构：
[1] Natl Taipei Univ, Dept Elect Engn, New Taipei 23741, Taiwan
来源：
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2021年 / 31卷 / 01期
关键词：
CMOS process; frequency synthesizer; phase-locked loop (PLL); MULTIPLIER;
D O I：
10.1109/LMWC.2020.3032285
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The design of an adjustable loop bandwidth (LBW) frequency synthesizer with an on-chip loop filter (LF) array is presented. The LF array based on the simple capacitor multiplier topology is proposed to support LBW switching between 500 kHz and 1 MHz while saving 82.9% chip size compared to the traditional LF array. The maximum capacitance of 108 pF is realized by using the capacitor multiplier with an on-chip capacitance of 6 pF. The proposed frequency synthesizer is implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-mu m CMOS process and supplied at 1.8 V with a current dissipation of 11.8 mA.
引用
收藏
页码：72 / 75
页数：4
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