82.5 GS/s (8 x 10.3 GHz Multi-Phase Clocks) Blind Over-Sampling Based Burst-Mode Clock and Data Recovery for 10G-EPON 10.3-Gb/s/1.25-Gb/s Dual-Rate Operation

We present an 82.5 GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5 GS/s over-sampling IC using 8 x 10.3 GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3 Gb/s and 1.25 Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-thex (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5 GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3 Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5 GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256 ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6 dBm at 10.3 Gb/s and -34 .6 dBm at 1.25 Gb/s and a high pulse-width distortion tolerance of +/-0.53 UI, which are superior to the 10G-EPON standard.