Range and Bitmask Analysis for Hardware Optimization in High-Level Synthesis

被引:0
|
作者
Gort, Marcel [1 ]
Anderson, Jason H. [1 ]
机构
[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON, Canada
来源
2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) | 2013年
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中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We consider the extent to which the bit-level representation of variables can be used to optimize hardware generated by high-level synthesis (HLS). Two approaches to bit-level optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to predetermine min/max ranges for variables to reduce the bitwidth required to represent variables in hardware. Bitmask analysis characterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don't-cares permit hardware to be eliminated under certain conditions. Static compiler-based analysis is contrasted with dynamic profiling-based analysis in terms of their potential to impact area and speed of HLS-generated hardware. For a set of benchmarks implemented in the Altera Cyclone II FPGA, results show bit-level optimizations in HLS based on static analysis reduce circuit area by 9%, on average, while additional optimizations based on dynamic analysis provide 34% area reduction.
引用
收藏
页码:773 / 779
页数:7
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