Parametric Yield Optimization Using Leakage-Yield-Driven Floorplanning

Continuous process scaling has resulted in ever-increasing process variations, which in turn cause severe parametric yield loss, e.g., timing & leakage yield loss. State-of-the-art methods optimize the leakage yield either by applying dual-vt or gate sizing technologies or by exploring the interdependency between leakage power and operating temperature. In this paper, we propose a novel leakage yield optimization method from another perspective, i.e., by exploring spatial correlations between leakage power of different modules. In our method, a very fast hierarchical leakage yield calculation method is introduced and integrated into a simulated annealing based floorplanner to build a leakage-yield-driven floorplanner, which can identify floorplans with optimized leakage yield. Experimental results show that our method significantly speeds up the leakage yield calculation by up to six orders of magnitude and the standard deviation of leakage can be reduced by up to 29% by applying our leakage-yield-driven floorplanning.