Tradsoff routing resource runtime and quality in buffered routing

被引:0
|
作者
Tang, XP [1 ]
Wong, MDF [1 ]
机构
[1] Cadence Design Syst, San Jose, CA 95134 USA
关键词
D O I
10.1109/ASPDAC.2004.1337613
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
With the wide use of hard macros and IP blocks in design, buffered routing (simultaneous routing and buffer insertion) becomes unavoidable. Routing resource allocation and distribution are serious concerns in buffered routing of deep submicron design. The capability of capturing the tradeoff between routing resource cost and signal delay is crucial in practice since the resource overuse of min-delay solution may cause congestion problem (congestion also means over-inserting buffers). However, many existing algorithms are mainly designed to minimize signal delay. In the paper, we first study the problem of minimizing the linear combination of delay and cost, and extend the graph-based algorithm in [10] to solve it. We then show that a variant of the algorithm can solve other problems such as maximizing delay reduction to cost ratio, minimizing routing cost subject to a delay constraint, and minimizing delay subject to the cost not exceeding a given budget. We also develop a hierarchical approach to buffered routing construction for problems with large number of sinks to tradeoff solution quality and runtime.
引用
收藏
页码:430 / 433
页数:4
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