Approaches to architecture-aware parallel scientific computation

被引:1
|
作者
Teresco, James A. [1 ]
Flaherty, Joseph E. [1 ]
Baden, Scott B. [1 ]
Faik, Jamal [1 ]
Lacour, Sibastien [1 ]
Parashar, Manish [1 ]
Taylor, Valerie E. [1 ]
Varela, Carlos A. [1 ]
机构
[1] Williams Coll, Dept Comp Sci, Williamstown, MA 01267 USA
基金
美国国家科学基金会; 美国能源部;
关键词
D O I
10.1137/1.9780898718133.ch3
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
引用
收藏
页码:33 / 58
页数:26
相关论文
共 50 条
  • [31] Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors
    Rafael Rodríguez-Sánchez
    Enrique S. Quintana-Ortí
    Journal of Real-Time Image Processing, 2017, 13 : 25 - 38
  • [32] Architecture-aware LDPC code design for software defined radio
    Zhu, Yuming
    Chaki-Abarti, Chaitali
    2006 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION, 2006, : 405 - 410
  • [33] A BiNoC architecture-aware task allocation and communication scheduling scheme
    Tsai, Wen-Chung
    Chen, Wei-De
    Lan, Ying-Cherng
    Hu, Yu-Hen
    Chen, Sao-Jie
    MICROPROCESSORS AND MICROSYSTEMS, 2016, 42 : 215 - 226
  • [34] ArchSampler: Architecture-Aware Memory Sampling Library for In-Memory Applications
    Zhou, Jian
    Wang, Jun
    2018 IEEE 36TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2018, : 258 - 265
  • [35] Enhanced MIH Architecture-aware Radio Resource Management Approach in NGWNs
    Ben Ali, Khitem
    Zarai, Faouzi
    Obaidat, Mohammad S.
    Kamoun, Lotfi
    2015 IEEE INTERNATIONAL CONFERENCE ON DATA SCIENCE AND DATA INTENSIVE SYSTEMS, 2015, : 611 - 616
  • [36] A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters
    Wang, Hui
    Isci, Canturk
    Subramanian, Lavanya
    Choi, Jongmoo
    Qian, Depei
    Mutlu, Onur
    ACM SIGPLAN NOTICES, 2015, 50 (07) : 93 - 106
  • [37] AWEDF: An Architecture-Aware Execution and Debugging Workflow for a Highly Reliable Chip
    Wang, Yuewei
    Gui, Qirui
    Wang, Meng
    Wang, Lizhe
    Zomaya, Albert Y.
    2017 IEEE 19TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS WORKSHOPS (HPCCWS): MULTICORE AND MULTITHREADED ARCHITECTURES AND ALGORITHMS (M2A2 2017), 2017, : 50 - 57
  • [38] Efficient Architecture-Aware Acceleration of BWA-MEM for Multicore Systems
    Vasimuddin, Md
    Misra, Sanchit
    Li, Heng
    Aluru, Srinivas
    2019 IEEE 33RD INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS 2019), 2019, : 314 - 324
  • [39] Architecture-aware configuration and scheduling of matrix multiplication on asymmetric multicore processors
    Sandra Catalán
    Francisco D. Igual
    Rafael Mayo
    Rafael Rodríguez-Sánchez
    Enrique S. Quintana-Ortí
    Cluster Computing, 2016, 19 : 1037 - 1051
  • [40] Architecture-aware low-density parity-check codes
    Mansour, MM
    Shanbhag, N
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 57 - 60