Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology

被引：0

作者：

Xu, L. ^{[1
]}

Cao, J. ^{[1
]}

Bhuva, B. L. ^{[1
]}

Chatterjee, I. ^{[2
]}

Wen, S. -J. ^{[3
]}

Wong, R. ^{[3
]}

Massengill, L. W. ^{[1
]}

机构：

[1] Vanderbilt Univ, Nashville, TN 37212 USA

[2] Airbus SE, Bremen, Germany

[3] Cisco Syst Inc, San Jose, CA USA

来源：

2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2019年

关键词：

Single-event upset; flip-flop; dual-well; triple-well; alpha particles; heavy ions;

D O I：

10.1109/irps.2019.8720514

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Triple-well designs provide excellent noise isolation in mixed-signal circuits. But the presence of deep-n-well significantly affects Single-Event (SE) response of these circuits. Comparison of dual-well and triple-well designs for recent technologies have shown inconsistent results. This paper presents SE response of dual-well and triple-well flip-flop (FF) designs at the 7-nm bulk FinFET node. Results show dual-well designs have significantly superior SE performance compared to triple-well designs over a wide range of supply voltages and for different particles. TCAD simulations for different depths of p-well show that collected charge increases when the depth of p-well decreases. The shallow p-well in the deep-n-well design results in strong charge confinement leading to increased SE cross sections.

引用

页数：5

共 33 条

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