Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach

被引:40
|
作者
Sharifi, Fazel [1 ]
Moaiyeri, Mohammad Hossein [1 ]
Navi, Keivan [1 ]
Bagherzadeh, Nader [2 ]
机构
[1] Shahid Beheshti Univ, Fac Elect & Comp Engn, Tehran, Iran
[2] Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA USA
关键词
Nanoelectronics; Multiple valued logic (MVL); CNTFET; Low-power design; MULTIPLE-VALUED LOGIC; TRANSISTORS INCLUDING NONIDEALITIES; COMPACT SPICE MODEL; CMOS CIRCUITS; POWER; NANOTECHNOLOGY; PERFORMANCE; ELECTRONICS; ADDERS; SPEED;
D O I
10.1016/j.mejo.2015.09.018
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs, such as having same mobility for electrons and holes and also capability of adopting desirable threshold voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise margins and higher robustness as compared to the previous CNTFET-based designs. The proposed quaternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45% lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42% and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs. (C) 2015 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1333 / 1342
页数:10
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