Negative and Positive Muon-induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs

被引：3

作者：

Liao, Wang ^{[1
]}

Hashimoto, Masanori ^{[1
]}

Manabe, Seiya ^{[2
]}

Watanabe, Yukinobu ^{[2
]}

Abe, Shin-ichiro ^{[3
]}

Nakano, Keita ^{[2
]}

Takeshita, Hayato ^{[2
]}

Tampo, Motonobu ^{[4
]}

Takeshita, Soshi ^{[4
]}

Miyake, Yasuhiro ^{[4
,5
]}

机构：

[1] Osaka Univ, Dept Informat Syst Engn, Suita, Osaka, Japan

[2] Kyushu Univ, Dept Adv Energy Engn Sci, Fukuoka, Fukuoka, Japan

[3] JAEA, Res Grp Radiat Transport Anal, Tokai, Ibaraki, Japan

[4] High Energy Accelerator Res Org KEK, Muon Sci Lab, Tokai, Ibaraki, Japan

[5] J PARC Ctr, Mat & Life Sci Div, Tokai, Ibaraki, Japan

来源：

2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2019年

基金：

日本学术振兴会;

关键词：

single event upset; SRAMs; muons; direct ionization; muon capture; technology scaling;

D O I：

10.1109/irps.2019.8720568

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we compare the negative and positive muon-induced SEU event cross sections of 28-nm and 65-nm planar bulk CMOS SRAMs. Our measurement results show a 3.6 X increase in muon-induced SEU event cross section from 65-nm to 28-nm technology, and negative muon-induced SEU event cross section is 3.3 X larger compared to positive muons at 28-nm technology. This result is consistent with the previous works reporting muon-induced SEU event cross section increases with technology scaling. The measured result also suggests the contribution of direct ionization to the total SEU event cross section is 54.1 % at 28-nm node with operating voltage of 0.6 V while it is 1.8 % at 65-nm node with 0.9 V.

引用

页数：5