Transient simulation of wire pull test on Cu/low-K wafers

被引:24
|
作者
Yeh, Chang-Lin [1 ]
Lai, Yi-Shao [1 ]
Kao, Chin-Li [1 ]
机构
[1] Adv Semicond Engn Inc, Stress Reliabil Lab, Kaohsiung 811, Taiwan
来源
IEEE TRANSACTIONS ON ADVANCED PACKAGING | 2006年 / 29卷 / 03期
关键词
Cu/low-K; finite-element analysis; wire pull test; wirebonding;
D O I
10.1109/TADVP.2006.875081
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper focuses on the numerical analysis of pull test reliability of gold wires bonded on the Cu/Iow-K wafer. Prior to wire pull, transient analysis of the complete wirebonding process, which involves both impact and ultrasonic vibration stages, is performed to allocate residual stresses within the wire and the Cu/low-K structure. After wirebonding, fracturing of the wire subjected to a pull load is modeled using the eroding technique so that failure patterns and bonding strength of the wire can be investigated. The analysis applies the explicit time integration scheme, which is feasible in dealing with nonlinear transient structural behavior. Parametric studies show that as the yield stress of the low-K material decreases, the pull force reduces significantly. Furthermore, the pull force increases as the bond force increases but not very significantly.
引用
收藏
页码:631 / 638
页数:8
相关论文
共 50 条
  • [31] Vibrational spectroscopy of low-k/ultra-low-k dielectric materials on patterned wafers
    Lam, Jeffrey C. K.
    Huang, Maggie Y. M.
    Tan, Hao
    Mo, Zhiqiang
    Mai, Zhihong
    Wong, Choun Pei
    Sun, Handong
    Shen, Zexiang
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A, 2011, 29 (05):
  • [32] Investigation of the mechanical characteristics of the Cu/low-k BEOL under wire bonding process loading
    Yuan, Cadmus C. A.
    Chang, H. M.
    Chiang, K. N.
    JOURNAL OF MECHANICS, 2022, 38 : 539 - 551
  • [33] 17.5um thin Cu wire bonding for fragile low-k wafer technology
    Jude, Teo Chen Kim
    2010 12th Electronics Packaging Technology Conference, EPTC 2010, 2010, : 355 - 358
  • [34] 17.5um Thin Cu Wire Bonding For Fragile Low-K Wafer Technology
    Jude, Teo Chen Kim
    2010 12TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2010, : 355 - 358
  • [35] Lithographic implications for Cu/low-k integration
    Mih, R
    Chen, N
    Jantzen, K
    Marsh, J
    Schneider, S
    OPTICAL MICROLITHOGRAPHY XII, PTS 1 AND 2, 1999, 3679 : 827 - 838
  • [36] Conduction processes in Cu/low-k interconnection
    Bersuker, G., 2000, IEEE, Piscataway, NJ, United States
  • [37] Techniques to improve Cu/low-k integration
    Shannon, V
    SOLID STATE TECHNOLOGY, 2001, : S22 - +
  • [38] Innovations needed for Cu/low-k integration
    不详
    SOLID STATE TECHNOLOGY, 2001, 44 (04) : 30 - +
  • [39] Role of Cu in TDDB of low-k dielectrics
    Lloyd, J. R.
    Ponoth, S.
    Liniger, E.
    Cohen, S.
    2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL, 2007, : 410 - +
  • [40] Dielectric integrity test for flip-chip devices with Cu/low-k interconnects
    Odegard, C
    Chiu, TC
    Hartfield, C
    Sundararaman, V
    55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings, 2005, : 1163 - 1171