Transient simulation of wire pull test on Cu/low-K wafers

被引:24
|
作者
Yeh, Chang-Lin [1 ]
Lai, Yi-Shao [1 ]
Kao, Chin-Li [1 ]
机构
[1] Adv Semicond Engn Inc, Stress Reliabil Lab, Kaohsiung 811, Taiwan
来源
关键词
Cu/low-K; finite-element analysis; wire pull test; wirebonding;
D O I
10.1109/TADVP.2006.875081
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper focuses on the numerical analysis of pull test reliability of gold wires bonded on the Cu/Iow-K wafer. Prior to wire pull, transient analysis of the complete wirebonding process, which involves both impact and ultrasonic vibration stages, is performed to allocate residual stresses within the wire and the Cu/low-K structure. After wirebonding, fracturing of the wire subjected to a pull load is modeled using the eroding technique so that failure patterns and bonding strength of the wire can be investigated. The analysis applies the explicit time integration scheme, which is feasible in dealing with nonlinear transient structural behavior. Parametric studies show that as the yield stress of the low-K material decreases, the pull force reduces significantly. Furthermore, the pull force increases as the bond force increases but not very significantly.
引用
收藏
页码:631 / 638
页数:8
相关论文
共 50 条
  • [1] Challenges of Cu Wire Bonding on Low-k/Cu Wafers with BOA Structures
    Lee, Chu-Chung
    Higgins, Leo M., III
    2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 342 - 349
  • [2] Transient analysis of the impact stage of wirebonding on Cu/low-K wafers
    Yeh, CL
    Lai, YS
    MICROELECTRONICS RELIABILITY, 2005, 45 (02) : 371 - 378
  • [3] Computational Modeling and Optimization for Wire Bonding Process on Cu/Low-K Wafers
    Huang, Weidong
    2009 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2009), 2009, : 268 - 276
  • [4] Failure Mode and Mechanism Analysis for Cu Wire Bond on Cu/Low-k Chip by Wire Pull Test and Finite-Element Analysis
    Che, Fa Xing
    Wai, Leong Ching
    Chai, Tai Chong
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2018, 18 (02) : 163 - 172
  • [5] Dynamic analysis of wirebonding process on Cu/low-K wafers
    Yeh, CL
    Lai, YS
    Wu, JD
    PROCEEDINGS OF 5TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, 2003, : 282 - 286
  • [6] Comprehensive dynamic analysis of wirebonding on Cu/low-K wafers
    Yeh, CL
    Lai, YS
    IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2006, 29 (02): : 264 - 270
  • [7] Probing the issues for Cu/low-k wire bonding
    Chylak, B
    Keller, F
    Levine, L
    SOLID STATE TECHNOLOGY, 2004, 47 (04) : 43 - +
  • [8] Direct Au and Cu wire bonding on Cu/Low-k BEOL
    Banda, P
    Ho, HM
    Whelan, C
    Lam, W
    Vath, CJ
    Beyne, E
    PROCEEDINGS OF THE 4TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2002), 2002, : 344 - 349
  • [9] Low-K wire bonding
    Kim, Yoon-joo
    Kim, Joon-soo
    Chung, Ji-young
    Na, Seok-ho
    Kim, Jin-young
    Kim, Seok-bong
    56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, : 1616 - +
  • [10] Noncontact electrical metrology of Cu/low-k interconnect for semiconductor production wafers
    Talanov, Vladimir V.
    Scherz, Andre
    Schwartz, Andrew R.
    APPLIED PHYSICS LETTERS, 2006, 88 (26)