Multicast FullHD H.264 Intra Video Encoder Architecture

被引:2
|
作者
Khan, Muhammad Usman Karim [1 ]
Shafique, Muhammad [1 ]
Bauer, Lars [1 ]
Henkel, Joerg [1 ]
机构
[1] Karlsruhe Inst Technol, Chair Embedded Syst, D-76131 Karlsruhe, Germany
关键词
Field programmable gate array (FPGA) implementation; FullHD video encoder; H.264; encoder; hardware sharing; multicast;
D O I
10.1109/TCAD.2015.2446933
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
High throughput demands have resulted in enormous increase in complexity of multicast video applications, which require multiple video encoders to simultaneously compress individual views. In this paper, we present an approach to encode independent videos using H.264 intra encoder on a single hardware platform, where the hardware resources are shared by independent encoders in a time-multiplexed manner. In addition to lowering the latency introduced by multicasting, we address the strong sequential data dependencies within the encoder. At 25 frames/s, 150 MHz prototype of the proposed encoder and multiple video capture/display on a mid-range field programmable gate array is also presented.
引用
收藏
页码:2049 / 2053
页数:5
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