On-chip calibration technique for delay line based bist jitter measurement

This paper describes an on-chip calibration technique for delay line based Time-to-Digital Converters (TDC) used in jitter measurement Built-in Self-Test (BIST). The proposed technique utilizes Pulse Width Modulation (PWM) to generate accurate voltages to control delay elements within the TDC. Calibration is performed in three stages; accuracy fine-tuning, measurement dynamic range adjustment, and characteristic curve generation. Preliminary simulation results using the calibration technique on a modified Vernier Delay Line (VDL) BIST provided a cycle-to-cycle jitter resolution of similar to5 ps. The calibration design consists of digital CMOS 2 components and has a potential die area of 0.03 mum(2). Calibration time is less than 1.1ms and only a single external calibration input pin is required in addition to the existing BIST.