Design of a Bus Voltage Digital Controller for a Dimmable Lighting System with Power Factor Correction

被引：0

作者：

Reginatto, P. ^{[1
]}

da Silva, M. F. ^{[1
]}

Seidel, A. R. ^{[1
]}

Alonso, J. M. ^{[2
]}

Polonskii, M. ^{[3
]}

Tambara, R. V. ^{[4
]}

机构：

[1] Univ Fed Santa Maria, GSEC, Eletr & Computat Syst Reserch & Dev Grp, Santa Maria, RS, Brazil

[2] Univ Oviedo, Elect & Elect Engn Dept, Gijon, Asturias, Spain

[3] Univ Passo Fundo, Dept Elect Engn, Passo Fundo, RS, Brazil

[4] Franciscan Univ Ctr, Dept Biomed Engn, Santa Maria, RS, Brazil

来源：

PROCEEDINGS OF THE IECON 2016 - 42ND ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY | 2016年

关键词：

PFC; dimming; fluorescent lamp; digital control;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a design of power factor correction (PFC) stage for a dimmable electronic ballast system to feed a T5 HE 28 W fluorescent lamp. The proposed topology is composed of a Single-Ended Primary Inductance Converter (SEPIC) used as a PFC stage with variable output voltage in order to supply a half-bridge inverter with an LCC filter controlled by a dedicated IR21592 integrated circuit. A novel dimming method based on controlling the output voltage of the PFC stage together with the variation of the half-bridge switching frequency in a narrow range is proposed and evaluated. A digital compensator design is presented in order to control the SEPIC output voltage. Experimental results for the PFC system are presented in order to test the operation of the entire illuminating system.

引用

页码：3337 / 3341

页数：5

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