A 1.4Gbit/s CMOS driver for 50 Omega ECL systems

被引：0
|
作者：
Navarro, J
Silveira, R
Romao, FL
VanNoije, WAM
机构：
来源：
SEVENTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/GLSV.1997.580404
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an output buffer which converts CMOS into ECL levels, and a brief analysis of its speed performance. The structure is designed in a 0.8 mu m CMOS process (effective length is 0.7 mu m). The circuit operation is based on current source switching. In the speed analysis we show that the speed is severely limited by the output load, and that the process, for common applications, is a secondary factor. Experimental results for the buffer operating at 1.4 Gbit/s rate are shown. The circuit is part of a 1.2 Gbit/s SDH/SONET system*.
引用
收藏
页码：14 / 18
页数：5
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