Novel logic circuits controlled by Vdd

被引:0
|
作者
Sekanina, Lukas [1 ]
Starecek, Lukas [1 ]
Kotasek, Zdenek [1 ]
机构
[1] Brno Univ Technol, Bozetechova 2, Brno, Czech Republic
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Polymorphic gates exhibit one or more additional functions in addition to the "main" function of the gate. The additional functions can be activated under certain conditions by changing control parameters (such as temperature, Vdd, light etc.) of the circuit. This paper shows a non-trivial polymorphic combinational circuit (5 bit majority/Boolean symmetry) which was designed at the gate level and then simulated using polymorphic NAND/NOR gates controlled by Vdd and some conventional gates at the transistor level. PSpice simulations have shown correct behavior of this circuit.
引用
收藏
页码:85 / +
页数:2
相关论文
共 50 条
  • [21] RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits
    Bhattacharya, Koustav
    Ranganathan, Nagarajan
    22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2009, : 453 - 458
  • [22] A Novel Crossing Device for in-plane Nanomagnetic Logic Circuits
    Nizer Rahmeier, Joao G.
    Resende, Tulio G.
    Melo, Luiz G. C.
    Vilela Neto, Omar P.
    2018 IEEE 18TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2018,
  • [23] Optically Controlled Ternary Logic Circuits Based on Organic Antiambipolar Transistors
    Panigrahi, Debdatta
    Hayakawa, Ryoma
    Fuchii, Kota
    Yamada, Yoichi
    Wakayama, Yutaka
    ADVANCED ELECTRONIC MATERIALS, 2021, 7 (01)
  • [24] Transistor Sizing and VDD Scaling for Low Power CMOS Circuits
    Kabbani, Adnan
    2009 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2009, : 93 - 96
  • [25] Heterojunction Negative-Capacitance Tunnel-FET as a Promising Candidate for Sub-0.4V VDD Digital Logic Circuits
    Guha, Sourav
    Pachal, Prithviraj
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2021, 20 : 576 - 583
  • [26] Logic Filter Cache for Wide-VDD-Range Processors
    Bardizbanyan, Alen
    Andersson, Oskar
    Rodrigues, Joachim
    Larsson-Edefors, Per
    23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 2016, : 376 - 379
  • [27] A novel technique to improve noise immunity of CMOS dynamic logic circuits
    Ding, L
    Mazumder, P
    41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004, 2004, : 900 - 903
  • [28] A Novel Voltage Controlled Crystal Oscillator (VCXO) Circuits
    Rohde, Ulrich L.
    Poddar, Ajay K.
    2009 IEEE 10TH ANNUAL WIRELESS AND MICROWAVE TECHNOLOGY CONFERENCE, 2009, : 175 - 180
  • [29] A Novel Leakage Reduction DOIND Approach For Nanoscale Domino Logic Circuits
    Shah, Ambika Prasad
    Neema, Vaibhav
    Daulatabad, Shreeniwas
    2015 EIGHTH INTERNATIONAL CONFERENCE ON CONTEMPORARY COMPUTING (IC3), 2015, : 434 - 438
  • [30] Novel serial-parallel converter using SFQ logic circuits
    Park, H.
    Yamanashi, Y.
    Taketomi, K.
    Yoshikawa, N.
    Fujimaki, A.
    Takagi, N.
    PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS, 2008, 468 (15-20): : 1977 - 1982