HDL constructs in linear word-level decision diagram based specification

被引：0

作者：

Wahid, K ^{[1
]}

Lu, DC ^{[1
]}

Rahman, C ^{[1
]}

机构：

[1] Univ Calgary, Dept Elect & Comp Engn, Calgary, AB, Canada

来源：

AUTOMATION AND REMOTE CONTROL | 2004年 / 65卷 / 06期

关键词：

Experimental Study; Mechanical Engineer; System Theory; Memory Requirement; Intermediate Format;

D O I：

10.1023/B:AURC.0000030903.92620.b1

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Linear Decision Diagrams (LDDs) are used in the paper as an intermediate format that allows us to quickly generate the circuit netlist from HDL (hardware description language), such as Verilog, or transform it to HDL description for further ASIC or FPGA synthesis and verification. The results of an extensive experimental study (on memory requirements, run time to convert LDD intermediate format to/from HDL, and verification via simulation) are reported here.

引用

页码：913 / 919

页数：7

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