Analysis of analog capacitor for mixed signal circuits in merged dynamic random access memory and logic devices

A poly-insulator-poly (PIP) analog capacitor with a novel structure is fabricated to minimize the number of process steps, by adopting an analog device in the merged dynamic random access memory (DRAM) and logic (MDL) process. It has polysilicon as the bottom electrode, which is used as the gate material of the transistor, and W-polycide as the top electrode, which is used and the leakage current is less as a bit line material in DRAM. The area capacitance without the fringe effect is 0.54 fF/mum(2) than 1 fA/mum(2). The minimum usable capacitor size without the fringe effect is 27 x 27 mum(2). The voltage coefficients of the 1st and 2nd order are 380 ppm/V and -11 ppm/V-2, respectively, where those of a conventional analog capacitor manufactured by the standard complementary metal oxide semiconductor (CMOS) process are 300-500 ppm/V and 10-50 ppm/V-2 , respectively. The matching value is 0.044% in an area of 27 x 27 mum(2), which is an excellent result compared with previous work.