Experimental and theoretical analysis of factors causing asymmetrical temperature dependence of Vt in High-k Metal gate CMOS with capped High-k techniques

Temperature (T) dependence of threshold voltage (V-t) for High-k Metal gate stack (HK/MG) CMOS is investigated thoroughly. It is found, for the first time, that T dependence of V-t (dV(t)/dT) for HK/MG CMOS shows asymmetrical behavior between N and PFETs unlike conventional Poly-Si/SiON CMOS. Moreover, this dV(t)/dT asymmetry is observed even if capping techniques for V-t tuning are applied to High-k dielectrics. The position of effective Fermi level in HK/MG (E-FM,E-eff) is determined quantitatively in a wide range of T by experimental and theoretical analysis for the first time, which reveals that the off-center arrangement of E-FM,E-eff in Si band gap is the cause of dV(t)/dT asymmetry not only in the long channel region but also in the short channel region. In addition, based on these analyses, dV(t)/dT for aggressively thinned FinFETs with HK/MG is predicted.