A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

The paper presents a novel 5.15 GHz-5.825 GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-mu m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843 mm(2). The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14 dB power conversion gain, -6 dBm input third-order intercept point (IIP3), 6.85 dB double side band (DSB) noise figure. The total mixer current is about 1.54 mA from 1.4 V supply voltage including output buffer. The total dc power consumption is 2.15 mW.