Estimating the Effect of Single-event Upsets on Microprocessors

被引：0
|
作者：
Constantinescu, Cristian [1 ]
Krishnamoorthy, Srini [2 ]
Nguyen, Tuyen [3 ]
机构：
[1] Adv Micro Devices Inc, Ft Collins, CO 80528 USA
[2] Adv Micro Devices Inc, Sunnyvale, CA 94088 USA
[3] Adv Micro Devices Inc, Austin, TX USA
来源：
PROCEEDINGS OF THE 2014 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS) | 2014年
关键词：
single-event upsets; soft errors; microprocessors;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Evaluating the impact of single-event upsets (SEUs) on complex VLSI circuits in general, and microprocessors in particular, requires an interdisciplinary approach, that includes soft error modeling, accelerated measurements, derating of the raw error rates, and specialized design tools. This paper discusses modeling techniques employed to estimate the soft error rates (SER) of storage cells, provides results of accelerated measurements for three technology nodes, and presents a technique for derating the raw error rates by simulated error injection. We use the measurement results to validate and calibrate the models. Then present the tool employed for deriving the SER of the Advanced Micro Devices processor code-named "Bulldozer" and examples of estimated SER. Our approach enables the cost-effective mitigation of SEU by employing data integrity protection for the most sensitive logic.
引用
收藏
页码：185 / 190
页数：6
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