A Model for the Free (Top) Surface Deformation of Through-Silicon Vias

Analytical models of stress and deformxation of through-silicon vias (TSV), relative to numerical ones, have the advantage of being inexpensive to evaluate and in providing insight. They have the additional advantage of allowing one to embed them in ECAD tools for real time design decisions. Motivated by this reasoning, in this paper, an analytical model for the three-dimensional state of stress in a periodic array of TSVs is developed. The model accounts for the onset of plasticity in the copper via and predicts the out-of-plane protrusion that occurs in the via due to differential thermal expansion with the surrounding Si matrix. Excessive out-of-plane deformation of the top surface of the via has the potential to induce fracture causing stress in the brittle dielectric layers that lie above the via. The predictions of the model are consistent with experimentally determined values reported in the literature. The process and design parameters that are critical to limiting the extent of protrusion are identified, and these in turn are used to develop design guidelines.