IF: An intermediate representation for SDL and its applications

被引:15
|
作者
Bozga, M [1 ]
Fernandez, JC [1 ]
Ghirvu, L [1 ]
Graf, S [1 ]
Krimm, JP [1 ]
Mounier, L [1 ]
Sifakis, J [1 ]
机构
[1] VERIMAG, Ctr Equat, F-38610 Gieres, France
关键词
SDL; time semantics; validation; model-checking; test generation; static analysis;
D O I
10.1016/B978-044450228-5/50028-X
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
We present work of a project for the improvement of a. specification/validation toolbox integrating a commercial toolset ObjectGEODE and different validation tools such as the verification tool CADP and the test sequence generator TGV. The intrinsic complexity of most protocol specifications lead us to study combinations of techniques such as static analysis and abstraction together with classical model-checking techniques. Experimentation and validation of our results in this context motivated the development of an intermediate representation for SDL called IF. In IF, a system is represented as a set of timed automata communicating asynchronously through a set of buffers or by rendez-vous through a set of synchronization gates. The advantage of the use of such a program level intermediate representation is that it is easier to interface with various existing tools, such as static analysis, abstraction and compositional state space generation. Moreover, it allows to define for SDL different, but mathematically sound, notions of time.
引用
收藏
页码:423 / 440
页数:18
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