Static random-access memory with embedded arithmetic logic units for in-memory computing and ternary content addressable memory operation

In-memory computing (IMC) is a novel computing architecture that presents considerable potential in solving the data transmission and energy consumption problems faced by the von Neumann architecture. The compound Boolean logic operation (CBLO) is a crucial component of most advanced computing platforms. This study presents a static random-access memory array structure comprising configurable embedded arithmetic logic units (ALUs), which can realize four types of CBLOs within a single cycle. The proposed structure can also form the ternary content addressable memory (TCAM) for ternary searching by configuring signal lines and sense amplifiers. The authors performed 5000 trials of the Monte Carlo simulation for four types of CBLOs. The results of all four types were observed to be accurate, and the delay of the TCAM was observed to be as low as 141 ps, which improves the parallelism of IMC, reduces power consumption, and significantly reduces calculation delay.