Efficient Utilization of SIMD Engines for General-Purpose Processors

This paper proposes stream model execution (SME), a new architectural technique that supports the efficient utilization of single-instruction multiple-data (SIMD) engines on general-purpose processors. SME adopts lightweight streaming processing as the intermediate representation. This process uses a hardware-software co-design approach to support efficient SIMD compilation and utilization. From a hardware perspective, the micro-architecture of SIMD engines is enabled for stream support to provide the key components to address the limitations of SIMD utilization, such as data rearrangement and non-consecutive memory access. Thus, sequential code can be compiled efficiently through a two-step procedure (i.e. Ccode -> SMECcode -> vectorized code) and then executed by the SME hardware. Our experimental evaluation shows that SME can outperform previous optimization techniques by an average of 58% for multimedia kernels and 26% for applications.