Efficient Hardware Accelerator for Compressed Sparse Deep Neural Network

被引：3

作者：

Xiao, Hao ^{[1
]}

Zhao, Kaikai ^{[1
]}

Liu, Guangzhu ^{[1
]}

机构：

[1] HeFei Univ Technol, Sch Microelect, Hefei, Peoples R China

来源：

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | 2021年 / E104D卷 / 05期

基金：

中国国家自然科学基金;

关键词：

deep neural networks; filed programmable gate array; run-length compression; sparse data;

D O I：

10.1587/transinf.2020EDL8153

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work presents a DNN accelerator architecture specifically designed for performing efficient inference on compressed and sparse DNN models. Leveraging the data sparsity, a runtime processing scheme is proposed to deal with the encoded weights and activations directly in the compressed domain without decompressing. Furthermore, a new data flow is proposed to facilitate the reusage of input activations across the fully-connected (FC) layers. The proposed design is implemented and verified using the Xilinx Virtex-7 FPGA. Experimental results show it achieves 1.99x, 1.95x faster and 20.38x, 3.04x more energy efficient than CPU and mGPU platforms, respectively, running AlexNet.

引用

页码：772 / 775

页数：4

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