Synthesis of analog CMOS circuits

被引：0
|
作者：
Shanker, KR
Vasudevan, V
机构：
来源：
TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/ICVD.1997.568173
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we describe an efficient method for transistor sizing in cell level analog circuits. An equation based method is used. SPICE quality device models are used and the sizing problem is posed as an optimisation problem. KCL, KVL and matching constraints are taken into account in the formulation of the optimisation problem without explicitly introducing them as constraints as was done previously. A tool developed based on th is method has been used to synthesise and study performance trade-offs in various CMOS op amps.
引用
收藏
页码：439 / 444
页数：6
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