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- [1] A Machine Learning-based Error Model of Voltage-Scaled Circuits 2020 50TH ANNUAL IEEE-IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS-SUPPLEMENTAL VOLUME (DSN-S), 2020, : 89 - 91
- [2] Work-in-Progress: DeVos: A Learning-based Delay Model of Voltage-Scaled Circuits INTERNATIONAL CONFERENCE ON COMPILERS, ARCHITECTURE, AND SYNTHESIS FOR EMBEDDED SYSTEMS (CODES +ISSS) 2019, 2019,
- [4] MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-scaled Circuits 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2018, : 159 - 165
- [5] b-HiVE: A Bit-Level History-Based Error Model with Value Correlation for Voltage-Scaled Integer and Floating Point Units 2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2015,
- [6] A Compressed and Accurate Sparse Deep Learning-based Workload-Aware Timing Error Model 2023 IEEE 41ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD, 2023, : 9 - 12
- [7] Reduced Error Model for Learning-based Calibration of Serial Manipulators ICINCO: PROCEEDINGS OF THE 17TH INTERNATIONAL CONFERENCE ON INFORMATICS IN CONTROL, AUTOMATION AND ROBOTICS, 2020, : 478 - 483
- [9] A Learning-Based Methodology for Accelerating Cell-Aware Model Generation PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, : 1580 - 1585
- [10] A Comprehensive Learning-Based Flow for Cell-Aware Model Generation 2022 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2022, : 484 - 488