b-HiVE: A Bit-Level History-Based Error Model with Value Correlation for Voltage-Scaled Integer and Floating Point Units

被引：15

作者：

Tziantzioulis, G. ^{[1
]}

Gok, A. M. ^{[1
]}

Faisal, S. M. ^{[2
]}

Hardavellas, N. ^{[1
]}

Ogrenci-Memik, S. ^{[1
]}

Parthasarathy, S. ^{[2
]}

机构：

[1] Northwestern Univ, Dept Elect Engn & Comp Sci, Evanston, IL USA

[2] Ohio State Univ, Dept Comp Sci, Columbus, OH 43210 USA

来源：

2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2015年

关键词：

Approximate Computing; Voltage Scaling; Error Modeling;

D O I：

10.1145/2744769.2744805

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Existing timing error models for voltage-scaled functional units ignore the effect of history and correlation among outputs, and the variation in the error behavior at different bit locations. We propose b-HiVE, a model for voltage-scaling-induced timing errors that incorporates these attributes and demonstrates their impact on the overall model accuracy. On average across several operations, b-HiVE's estimation is within 1-3% of comprehensive analog simulations, which corresponds to 5-17x higher accuracy (6-10x on average) than error models currently used in approximate computing research. To the best of our knowledge, we present the first bit-level error models of arithmetic units, and the first error models for voltage scaling of bitwise logic operations and floating-point units.

引用

页数：6