Delay analysis and optimal biasing for high speed low power current mode logic circuits

被引：0

作者：

Kakani, V ^{[1
]}

Dai, FF ^{[1
]}

Jaeger, RC ^{[1
]}

机构：

[1] Auburn Univ, Dept Elect & Comp Engn, Auburn, AL 36849 USA

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a delay analysis for Current Mode Logic (CML) circuits operating at the GHz range. The optimal biasing for CML circuits is obtained considering the circuit speed and power consumption. We propose and analyze a novel "keep alive" CML circuit that biases the upper level transistors at the slightly higher current than the lower level transistors. A speed improvement of about 11% at low bias range is demonstrated using the proposed biasing scheme.

引用

页码：869 / 872

页数：4

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