A 6 mW 750 MHz anti-aliasing filter for receiver analog front-end

被引：0

作者：

Lo, Chi-Hsiang ^{[1
]}

机构：

[1] Natl Ilan Univ, Dept Elect Engn, Ilan, Taiwan

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2014年 / 79卷 / 03期

关键词：

Filter; AFE; IM3;

D O I：

10.1007/s10470-014-0293-1

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low power high speed continuous-time filter for receiver application in standard 90 nm CMOS process is presented. A biquad cell based on the open-loop topology is implemented. Besides, a differential voltage buffer with additional gain boost, high linear voltage-to-voltage conversion and low output impedance is introduced. In this work, a fourth-order filter is implemented. Simulation results show the 750 MHz cutoff frequency with less than -50 dB IM3 for a 300 mVpp input. The power consumption for this filter is 6 mW at a 1.2-V supply.

引用

页码：599 / 604

页数：6

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