All-Digital High-Resolution PWM With a Wide Duty-Cycle Range

被引：0
|
作者：
Morales, Juan I. [1 ]
Chierchie, Fernando [1 ]
Mandolesi, Pablo S. [1 ,2 ]
Paolini, Eduardo E. [1 ,2 ]
机构：
[1] UNS, CONICET, Dept Ing Elect & Comp, Inst Invest Ing Elect IIIE Alfredo Desages, Bahia Blanca, Buenos Aires, Argentina
[2] CIC Prov Buenos Aires, La Plata, Buenos Aires, Argentina
来源：
2019 ARGENTINE CONFERENCE ON ELECTRONICS (CAE) | 2019年
关键词：
Pulse-width modulation (PWM); delay-line; CMOS integrated circuits; high-resolution; programmable delay; DELAY-LINE;
D O I：
10.1109/cae.2019.8709295
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An all-digital high-resolution pulse-width modulator in standard 130-nm CMOS technology is presented in this work. The architecture is based on a digitally-controlled delay element with variable time interval up to 50 ps and adjustable against process, voltage and temperature (PVT) variations. Post-layout simulation results show a linear response between the control word and delay. The PWM modulator uses several delay elements in a hybrid configuration that allows to obtain duty cycles with 18-bit resolution, without using a high-frequency internal clock while maintaining low power consumption.
引用
收藏
页码：15 / 20
页数：6
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