Fast 32-channel readout chip with counters for GEMs, APDs and MGCs

被引：0

作者：

Hollander, RW ^{[1
]}

van Eijk, WE ^{[1
]}

Huizenga, J ^{[1
]}

Lubking, GW ^{[1
]}

de Gans, D ^{[1
]}

Schelen, JBJ ^{[1
]}

机构：

[1] Delft Univ Technol, Inst Interfac Reactor, Radiat Technol Dept, NL-2629 JB Delft, Netherlands

来源：

2001 IEEE NUCLEAR SCIENCE SYMPOSIUM, CONFERENCE RECORDS, VOLS 1-4 | 2002年

关键词：

D O I：

10.1109/NSSMIC.2001.1009677

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

New bright radiation sources like the new generation spallation sources, require fast detectors and fast readout electronics. Position sensitive detectors for imaging applications will be segmented and data rates of 10(7) s(-1) per readout channel are envisaged. We are developing a 32-channel self triggering fast readout chip, with two 24-bit 100 MHz counters per channel. Per chip one calibration input, the analog output of one selectable channel and the common OR-ed comparator output are available for testing and calibration. The common comparator threshold is set on chip with a DAC. Noisy channels can be disabled. Two counters per channel are implemented for off-line correction of 2-channel clusters. Most parts of the chip are tested and some are available as separate chips. On the 8 channel preamplifier-shaper chip for each channel a 50 Omega output buffer has been added. Rise and fall times of 2.4 ns and 7.6 ns respectively have been obtained.

引用

页码：797 / 799

页数：3

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