High-Speed Implementation of PRESENT on AVR Microcontroller

被引:5
|
作者
Kwon, Hyeokdong [1 ]
Kim, Young Beom [2 ]
Seo, Seog Chung [2 ,3 ]
Seo, Hwajeong [1 ]
机构
[1] Hansung Univ, Div IT Convergence Engn, Seoul 136792, South Korea
[2] Kookmin Univ, Dept Financial Informat Secur, Seoul 02707, South Korea
[3] Kookmin Univ, Dept Informat Secur Cryptol & Math, Seoul 02707, South Korea
基金
新加坡国家研究基金会;
关键词
PRESENT; counter mode of operation; AVR; software implementation;
D O I
10.3390/math9040374
中图分类号
O1 [数学];
学科分类号
0701 ; 070101 ;
摘要
We propose the compact PRESENT on embedded processors. To obtain high-performance, PRESENT operations, including an add-round-key, a substitute layer and permutation layer operations are efficiently implemented on target embedded processors. Novel PRESENT implementations support the Electronic Code Book (ECB) and Counter (CTR). The implementation of CTR is improved by using the pre-computation for one substitute layer, two diffusion layer, and two add-round-key operations. Finally, compact PRESENT on target microcontrollers achieved 504.2, 488.2, 488.7, and 491.6 clock cycles per byte for PRESENT-ECB, 16-bit PRESENT-CTR (RAM-based implementation), 16-bit PRESENT-CTR (ROM-based implementation), and 32-bit PRESENT-CTR (ROM-based implementation) modes of operation, respectively. Compared with former implementation, the execution timing is improved by 62.6%, 63.8%, 63.7%, and 63.5% for PRESENT-ECB, 16-bit PRESENT-CTR (RAM based implementation), 16-bit PRESENT-CTR (ROM-based implementation), and 32-bit PRESENT-CTR (ROM-based implementation) modes of operation, respectively.
引用
收藏
页码:1 / 16
页数:15
相关论文
共 50 条
  • [41] Implementation of a high-speed network for the DFN-community
    Kaufmann, Peter
    Computer networks and ISDN systems, 1995, 26 (Suppl 4):
  • [42] High-Speed ASIC Implementation of Paillier Cryptosystem with Homomorphism
    Cai, Chun
    Awano, Hiromitsu
    Ikeda, Makoto
    2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,
  • [43] Implementation of high-speed SHA-1 architecture
    Lee, Eun-Hee
    Lee, Je-Hoon
    Park, Il-Hwan
    Cho, Kyoung-Rok
    IEICE ELECTRONICS EXPRESS, 2009, 6 (16): : 1174 - 1179
  • [44] Novel systolic implementation of the high-speed adaptive filter
    Shang, Yong
    Wu, Shunjun
    Xiang, Haige
    Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology, 2002, 24 (08):
  • [45] High-speed VLSI implementation of IIR lattice filters
    Feiste, KA
    Swartzlander, EE
    THIRTIETH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1997, : 1057 - 1062
  • [47] High-Speed Implementation of MultiMCW Entropy Estimation Method
    Kim, Wontae
    Park, Hojoong
    Yeom, Yongjin
    Kang, Ju-Sung
    2017 IEEE CONFERENCE ON APPLICATION, INFORMATION AND NETWORK SECURITY (AINS), 2017, : 60 - 63
  • [48] High-Speed Hardware Implementation of Rainbow Signature on FPGAs
    Tang, Shaohua
    Yi, Haibo
    Ding, Jintai
    Chen, Huan
    Chen, Guomin
    POST-QUANTUM CRYPTOGRAPHY, 2011, 7071 : 228 - +
  • [49] Block implementation of high-speed adaptive noise canceller
    Wu, XH
    Li, S
    Takahashi, N
    Takebe, T
    ICSP '96 - 1996 3RD INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, PROCEEDINGS, VOLS I AND II, 1996, : 595 - 598
  • [50] VLSI Implementation of High-speed SHA-256
    Bai, Ling
    Li, Shuguo
    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 131 - +