Advances In Vertical Solid-State Current Limiters For Individual Field Emitter Regulation In High-Density Arrays

We report the design, fabrication, and characterization of improved solid-state elements intended for individual regulation of field emitters part of high-density arrays. We demonstrate a high-yield, CMOS compatible fabrication process of single-crystal, vertical, ungated, n-type silicon field-effect transistors (FETs); each device behaves as a current source when is biased at a voltage larger than its drain-source saturation voltage. An ungated FET in saturation connected in series to a field emitter can compensate for the wide variation in current-voltage characteristics of the field emitters due to the tip radii spread present in any field emitter array, which should result in emitter burn-out protection, larger array utilization, and smaller array emission non-uniformity. Using 1-2 Omega.cm single-crystal n-Si wafers, we fabricated arrays of 25 mu m tall vertical ungated FETs with 0.5 mu m diameter that span two orders of magnitude of array size. Experimental characterization of the arrays demonstrates that the current is limited with > 3.5 V bias voltage to the same similar to 6 mu A (6 A.cm(-2)) per-FET value. Finite element simulations of the device predict a saturation voltage close to the experimental value and a saturation current within a factor of two of the experimental value.