Integrated parametric timing optimization of digital systems

Clock skew optimization is a timing technique to improve system performance by employing scheduled skews at flip-flops, The integrated framework presented here includes a new linear programming (LP) formulation for the clock skew optimization problem, In this work, we use the concept of a global time frame, instead of a local one, to find a set of optimal skews to minimize system cycle time, The framework provides a firm theoretical foundation for scheduling skews into existing designs. Furthermore, we extend the LP formulation to accommodate retiming in the optimization process. Our framework allows for concurrent timing optimization of a design by retiming the circuit and scheduling clock skews at flip-flops. It is shown that this optimization can be formulated as a mixed-integer linear program and significantly reduce the clock period.