共 50 条
- [32] Tearing based automatic abstraction for CTL model checking 1996 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, 1996, : 76 - 81
- [33] Symbolic computation tree logic model checking of time Petri nets Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 1997, 80 (04): : 11 - 20
- [34] Symbolic model checking of Verilog programs with the propositional projection temporal logic Xi'an Dianzi Keji Daxue Xuebao/Journal of Xidian University, 2014, 41 (02): : 79 - 84
- [36] Application of symbolic and bounded model checking to the verification of logic control systems ETFA 2005: 10TH IEEE INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION, VOL 1, PTS 1 AND 2, PROCEEDINGS, 2005, : 247 - 250
- [37] CTL model checking based on forward state traversal 1996 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, 1996, : 82 - 87
- [38] Symbolic computation tree logic model checking of time Petri nets ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 1997, 80 (04): : 11 - 20