Behavioral Modelling and Optimization of a Cyclic Feedback-Based Successive Approximation TDC with Dynamic Delay Equalization

This paper investigates the performance of cyclic feedback-based Successive Approximation Time-to-Digital Converter (SA-TDC) with dynamic delay equalization aimed to improve its conversion speed. The converter architecture is studied through numerical and behavioral modelling simulations presenting relevant implementation details and the impact of circuit non-idealities such as devices mismatch and noise. A comprehensive investigation of the dynamic delay equalization technique provides useful insights on the nominal achievable performance (i.e. effective time resolution), as well as circuit implementation guidelines. Furthermore, two novel alternative SA TDC topologies are proposed, targeting superior power efficiency with negligible hardware overhead.