Dynamic Equalization of Logic Delays in Feedback-Based Successive Approximation TDCs

The paper is focused on a development of a feedback-based architecture for successive-approximation time-to-digital converter (SA-TDC). The adoption of the feedback-based rather than feedforward architecture for the n-bit SA-TDCs is inspired by the classic successive approximation voltage-to-digital converter and motivated by a possible reduction of the number of time comparators from n to one. Nevertheless, existing developments of the feedback-based SA-TDC are characterized by much longer conversion time than that for feedforward SA-TDCs. In the paper, a concept of the feedback-based SA-TDC with dynamic equalization of logic propagation delays in the feedback loops is presented. The use of this technique allows to maintain the conversion time of the feedback-based SA-TDC the same as for the feedforward SA-TDC with just a single time comparator.