High-voltage stress test paradigms of analog CMOS ICs for gate-oxide reliability enhancement

被引：12

作者：

Khalil, MA ^{[1
]}

Wey, CL ^{[1
]}

机构：

[1] Michigan State Univ, Dept Elect & Comp Engn, E Lansing, MI 48824 USA

来源：

19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/VTS.2001.923458

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents the first-ever research on high-voltage stress of analog circuits to enhance their oxide reliability and to reduce the manufacturing cost, The emphasis of this paper is placed on how to properly stress analog circuits and the development of efficient algorithms for generating stress vectors that meet the stress coverage requirement within a feasible stress time.

引用

页码：333 / 338

页数：6

共 50 条

[21] From wafer-level gate-oxide reliability towards ESD failures in advanced CMOS technologies
Kerber, A
Röhner, M
Wallace, C
O'Riain, L
Kerber, M
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (04) : 917 - 920
[22] AN ANALOG TECHNOLOGY INTEGRATES BIPOLAR, CMOS, AND HIGH-VOLTAGE DMOS TRANSISTORS
KRISHNA, S
KUO, J
GAETA, IS
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (01) : 89 - 95
[23] Design and experimental demonstration of high-voltage lateral nMOSFETs and high-temperature CMOS ICs*
Isukapati, Sundar Babu
Zhang, Hua
Liu, Tianshi
Gupta, Utsav
Ashik, Emran
Morgan, Adam J.
Jang, Seung Yup
Lee, Bongmook
Sung, Woongje
Fayed, Ayman
Agarwal, Anant K.
MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2024, 169
[24] A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes
Ker, MD
Chen, SL
Tsai, CS
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2004, : 321 - 324
[25] Carrier injection efficiency for the reliability study of 3.5-1.2 nm thick gate-oxide CMOS technologies
Bravaix, A
Trapes, C
Goguenheim, D
Revil, N
Vincent, E
MICROELECTRONICS RELIABILITY, 2003, 43 (08) : 1241 - 1246
[26] Reliability of HTO based high-voltage gate stacks for flash memories
Raskin, Yosef
Salameh, Asaad
Betel, David
Roizin, Yakov
MICROELECTRONICS RELIABILITY, 2007, 47 (4-5) : 615 - 618
[27] Electrical Characterization and Reliability of Split-Gate High-Voltage Transistors
Manzini, Stefano
Rossetti, Mattia
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2018, 18 (02) : 279 - 283
[28] High-voltage low-power analog design in nanometer CMOS technologies
Bazaijani, Seyfi
Mathe, Lennart
Yuan, Dana
Hinrichs, Jeff
Miao, Guoqing
PROCEEDINGS OF THE 2007 IEEE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING (BCTM), 2007, : 149 - 154
[29] Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection
Chen, Wen-Yi
Ker, Ming-Dou
Jou, Yeh-Ning
Huang, Yeh-Jen
Lin, Geeng-Lih
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 385 - +
[30] Reliability for Pure CMOS One-time Programmable Memory Using Gate-Oxide Anti-fuse (eFuse)
Wakai, Nobuyuki
ISTFA 2008: CONFERENCE PROCEEDINGS FROM THE 34TH INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, 2008, : 349 - 353

← 1 2 3 4 5 →