Reconfigurable processing: The solution to low-power programmable DSP

被引：0
|
作者：
Rabaey, JM
机构：
来源：
1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V: VOL I: PLENARY, EXPERT SUMMARIES, SPECIAL, AUDIO, UNDERWATER ACOUSTICS, VLSI; VOL II: SPEECH PROCESSING; VOL III: SPEECH PROCESSING, DIGITAL SIGNAL PROCESSING; VOL IV: MULTIDIMENSIONAL SIGNAL PROCESSING, NEURAL NETWORKS - VOL V: STATISTICAL SIGNAL AND ARRAY PROCESSING, APPLICATIONS | 1997年
关键词：
D O I：
暂无
中图分类号：
O42 [声学];
学科分类号：
070206 ; 082403 ;
摘要：
One of the most compelling issues in the design of wireless communication components is to keep power dissipation between bounds. While low-power solutions are readily achieved in an application-specific approach, doing so in a programmable environment is a substantially harder problem. This paper presents an approach to low-power programmable DSP that is based on the dynamic reconfiguration of hardware modules. This technique has shown to yield at least an order of magnitude of power reduction compared to traditional instruction-based engines for problems in the area of wireless communication.
引用
收藏
页码：275 / 278
页数：4
相关论文
共 50 条
  • [21] Approaches to low-power implementations of DSP systems
    Parhi, KK
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2001, 48 (10) : 1214 - 1224
  • [22] DSP datapath synthesis for low-power applications
    Chiou, LY
    Muhammand, K
    Roy, K
    2001 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-VI, PROCEEDINGS: VOL I: SPEECH PROCESSING 1; VOL II: SPEECH PROCESSING 2 IND TECHNOL TRACK DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS NEURALNETWORKS FOR SIGNAL PROCESSING; VOL III: IMAGE & MULTIDIMENSIONAL SIGNAL PROCESSING MULTIMEDIA SIGNAL PROCESSING, 2001, : 1165 - 1168
  • [23] Low-power VLSI synthesis of DSP systems
    Sharma, S
    Attri, S
    Chauhan, RC
    INTEGRATION-THE VLSI JOURNAL, 2003, 36 (1-2) : 41 - 54
  • [24] A Flexible Low Power DSP With a Programmable Truncated Multiplier
    Solaz, Manuel de la Guia
    Han, Wei
    Conway, Richard
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (11) : 2555 - 2568
  • [25] A novel low-power reconfigurable FFT processor
    Zhao, YT
    Erdogan, AT
    Arslan, T
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 41 - 44
  • [26] Low-power, reconfigurable adaptive equalizer architecture
    Univ of Illinois at Urbana-Champaign, Urbana, United States
    Conf Rec Asilomar Conf Signals Syst Comput, (1391-1395):
  • [27] Dynamic algorithm transformations (DAT) - A systematic approach to low-power reconfigurable signal processing
    Goel, M
    Shanbhag, NR
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1999, 7 (04) : 463 - 476
  • [28] A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing
    Guerrieri, Andrea
    Kashani-Akhavan, Sahand
    Lombardi, Pasquale
    Belhadj, Bilel
    Ienne, Paolo
    2018 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS 2018), 2018, : 74 - 81
  • [29] Dynamic algorithm transformations (DAT) - a systematic approach to low-power reconfigurable signal processing
    Univ of Illinois at Urbana-Champaign, Urbana, United States
    IEEE Trans Very Large Scale Integr VLSI Syst, 4 (463-476):
  • [30] An automated, reconfigurable, low-power RFID tag
    Jones, Alex K.
    Hoare, Raymond R.
    Dontharaju, Swapna R.
    Tung, Shenchih
    Sprang, Ralph
    Fazekas, Josh
    T Cain, James
    Mickle, Marlin H.
    43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, : 131 - +
12345