Implementing Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Squares Codes

被引:0
|
作者
Reviriego, P. [1 ]
Liu, S. [1 ]
Maestro, J. A. [1 ]
Lee, S. [2 ]
Touba, N. A. [3 ]
Datta, R. [3 ]
机构
[1] Univ Antonio de Nebrija, Madrid, Spain
[2] Seoul Natl Univ Sci & Technol, Seoul, South Korea
[3] Univ Texas Austin, Austin, TX 78712 USA
来源
PROCEEDINGS OF THE 2013 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS) | 2013年
关键词
Error correction codes; majority logic decoding; memory; Multiple Cell Upsets (MCUs);
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MC:Us more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) arc used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.
引用
收藏
页码:167 / 171
页数:5
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