Synthesizing Hardware from Dataflow Programs

被引：32

作者：

Janneck, Joern W. ^{[2
]}

Miller, Ian D. ^{[3
]}

Parlour, David B. ^{[4
]}

Roquier, Ghislain ^{[5
]}

Wipliez, Matthieu ^{[1
]}

Raulet, Mickael ^{[1
]}

机构：

[1] IETR INSA, CNRS, UMR 6164, F-35043 Rennes, France

[2] Xilinx Inc, San Jose, CA 95124 USA

[3] siXis Inc, Res Triangle Pk, NC 27709 USA

[4] Tabula Inc, Santa Clara, CA 95054 USA

[5] Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland

来源：

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2011年 / 63卷 / 02期

关键词：

Dataflow; CAL; Reconfigurable Video Coding; MPEG; High-level synthesis;

D O I：

10.1007/s11265-009-0397-5

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal. The paper presents a code generator producing RTL targeting FPGAs for Cal, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.

引用

页码：241 / 249

页数：9

共 50 条

[41] Generating Example Data for Dataflow Programs
Olston, Christopher
Chopra, Shubham
Srivastava, Utkarsh
ACM SIGMOD/PODS 2009 CONFERENCE, 2009, : 245 - 256
[42] Causal dataflow analysis for concurrent programs
Farzan, Azadeh
Madhusudan, P.
TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANALYSIS OF SYSTEMS, PROCEEDINGS, 2007, 4424 : 102 - +
[43] SYNTHESIZING DELAY INSENSITIVE CIRCUITS FROM VERIFIED PROGRAMS
HULGAARD, H
CHRISTENSEN, PH
STAUNSTRUP, J
LECTURE NOTES IN COMPUTER SCIENCE, 1992, 574 : 326 - 337
[44] Analysing Dataflow Programs with Causation Traces
Boulasikis, Michail
Gruian, Flavius
Callanan, Gareth
Janneck, Jorn W.
PROCEEDINGS OF THE 2022 31ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PACT 2022, 2022, : 534 - 535
[45] Partitioning and Mapping Dynamic Dataflow Programs
Arslan, Mehmet Ali
Janneck, Jorn W.
Kuchcinski, Krzysztof
2012 CONFERENCE RECORD OF THE FORTY SIXTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS (ASILOMAR), 2012, : 1452 - 1456
[46] Dataflow testing of Java programs with DFC
Institute of Computer Science, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland
Lect. Notes Comput. Sci., 1600, (215-228):
[47] A Complete Language for Faceted Dataflow Programs
Delpeuch, Antonin
ELECTRONIC PROCEEDINGS IN THEORETICAL COMPUTER SCIENCE, 2020, (323): : 1 - 14
[48] Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs
Savas, Suleyman
Ul-Abdin, Zain
Nordstrom, Tomas
COMPUTERS, 2018, 7 (02)
[49] Exposing ILP in Custom Hardware with a Dataflow Compiler IR
Zaidi, Ali Mustafa
2013 22ND INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT), 2013, : 411 - 411
[50] An automated process for compiling dataflow graphs into reconfigurable hardware
Rinker, R
Carter, M
Patel, A
Chawathe, M
Ross, C
Hammes, J
Najjar, WA
Böhm, W
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2001, 9 (01) : 130 - 139

← 1 2 3 4 5 →