Modeling the gate Tunneling current effects of sub100nm NMOS devices with an ultra-thin (1nm) gate oxide

被引：0

作者：

Kuo, James B. ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei, Taiwan

来源：

2007 International Workshop on Electron Devices and Semiconductor Technology | 2007年

关键词：

D O I：

10.1109/EDST.2007.4289773

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports the modelling the gate tunneling current effects of sub-100nm NMOS devices with an ultra-thin (1nm) gate oxide. As verified by the experimentally measured data, the compact gate tunneling current model considering the distributed effect provides an accurate prediction of the gate, source, and drain currents for the device biased in triode and saturation regions. Based on the compact model, the negative gate current could be successfully explained as a result of the opposite direction of the local vertical electric field in the gate oxide near drain.

引用

页码：37 / 40

页数：4

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