Floating-point fused multiply-add architectures

Two new floating-point fused multiply-add architectures for the single instruction execution of (A x B) + C are presented. The three-path architecture uses parallel hardware paths similar to those in dual-path floating-point adders. The new bridge architecture re-uses common floating-point components to add a fused multiply-add instruction. Each new architecture as well as 2 collection of floating-point arithmetic units and a classic fused multiplier-adder have been designed using the Advanced Micro Devices 65 nanometer silicon on insulator CMOS technology to fairly compare the new architectures.