Chip scale 3-D topography synthesis

被引：3

作者：

Niewczas, M ^{[1
]}

Li, XL ^{[1
]}

Strojwas, A ^{[1
]}

Maly, W ^{[1
]}

机构：

[1] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA

来源：

OPTICAL MICROLITHOGRAPHY XI | 1998年 / 3334卷

关键词：

topography; 3-D lithography modeling; printability analysis; pattern matching;

D O I：

10.1117/12.310811

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We propose a novel approach to perform the chip scale mask to topography mapping by building a library of repetitive mask patterns. We call them vicinity patterns. They describe a collection of mask features in close proximity. This pattern library is used to synthesize 3-D topography of an arbitrary part of the chip topography. We define some process-related parameters, which we call critical interaction lengths, as a basis for mask decomposition into the vicinity patterns.

引用

页码：785 / 794

页数：4

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